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semicustom products ut0.6 m cr h/ srh commercial radhard tm and strategic radhard tm gate array family data sheet may 2002 features q multiple gate array sizes up to 600,000 usable equivalent gates q toggle rates up to 150 mhz q advanced 0.6 m ( 0.5 m l eff ) radiation-tolerant silicon gate cmos processed in a commercial fab q operating voltage of 5v and /or 3.3v q qml class q & v compliant q designed specifically for high reliability applications q commercial radhard tm for r adiation-tolerant to 300k rads to meet space requirements and seu-immune to less than 2 .0e-10 errors/bit-day q strategic radhard tm for radiation environments to 1 mega rads to meet space requirements and seu-immune to less than 2.0e-10 errors/bit-day q jtag (ieee 1149.1) boundary-scan supported q low noise package technology for high speed circuits q design support using mentor graphics? and synopsys tm in vhdl or verilog design languages on sun? and linux workstations q supports cold sparing fo r p ower down applications q supports voltage translation - 5v bus to 3.3v bus - 3.3v bus to 5v bus product description the high-performance ut0.6 m crh /srh gate array family features densities up to 600,000 equivalent gates and is avail- able in mil-prf-38535 qml q and v product assurance levels and is radiation-tolerant. the commercial radhard tm and strategic radhard tm sili- con is fabricated at american microsystems incorporated (ami) using a minimally invasive processing module, devel- oped by utmc, that enhances the total dose radiation hardness of the field and gate oxides while maintaining circuit density and reliability. in addition, for both greater transient radiation-hardness and latchup immunity, the utmc 0.6 m process is built on epitaxial substrate wafers. developed using utmc?s patented architectures, the ut0.6 m crh /srh gate array family uses a highly efficient continuous column transistor architecture for the internal cell construction. combined with state-of-the-art placement and routing tools, the utilization of available transistors is maxi- mized using three levels of metal interconnect. the ut0.6 m crh /srh family of gate arrays is supported by an extensive cell library that includes ssi, msi, and 54xx equivalent functions, as well as configurable ram and cores. utmc?s core library includes the following functions: intel 80c31? equivalent intel 80c196? equivalent mil-std-1553 functions (brctm, rti, rtmp) mil-std-1750 microprocessor risc microcontroller configurable ram (sram, dpsram) u sa rt (8 2 c51) ed ac
2 table 1. gate densities notes: 1. based on nand2 equivalents. actual usable gate count is design-dependent. estimates reflect a mix of functions including ram. 2. includes five pins that may or may not be reserved for jtag boundary-scan, depending on user requirements. 3. reserved for dedicated v dd /v ss and v ddq /v ssq . low-noise device and package solutions the ut0.6 m cr h/srh array family?s output drivers feature pro- grammable slew rate control for minimizing noise and switching transients. this feature allows the user to optimize edge charac- teristics to match system requirements. separate on-chip power and ground buses are provided for internal cells and output driv- ers which further isolate internal design circuitry from switching noise. in addition, aeroflex utmc offers advanced low-noise package technology with multi-layer, co-fired ceramic construction fea- turing built-in isolated power and ground planes (see table 2) . these planes provide lower overall resistance/inductance through power and ground paths which minimize voltage drops during periods of heavy switching. these isolated planes also help sustain supply voltage during dose rate events, thus prevent- ing rail span collapse. flatpacks are available with up to 3 52 leads; pgas are available with up to 299 pins and l gas to 472 pins. aeroflex utmc?s flatpacks feature a non-conductive tie bar that helps maintain lead integrity through test and handling operations. in addition to the packages listed in table 2, aeroflex utmc offers custom package development and package tooling modification services for individual requirements. device part numbers equivalent usable gates 1 signal i/o 2 power & ground pads 3 ut06mra010 10,000 58 6 ut06mra0 25 2 5,000 1 92 4 8 ut 06mra050 50,000 1 92 4 8 ut 06mra075 75,000 308 76 ut 06mra100 100,000 308 76 ut06mra1 50 150,000 308 76 u t06mra2 00 200,000 432 96 ut 06mra2 50 250,000 4 32 96 ut 06mra3 00 300,000 4 32 96 ut 06mra3 50 350,000 4 32 96 ut 06mra4 00 400,000 544 144 ut 06mra4 50 450,000 544 1 44 ut 06mra5 00 500,000 544 1 44 ut 06mra5 50 550,000 544 1 44 ut 06mra6 00 600,000 544 1 44
3 table 2. packages notes: 1. the number of device i/o pads available may be restricted by the selected package. 2. pga packages have one additional non-connected index pin (i.e., 84 + 1 index pin = 85 total package pins for the 85 pga). contact aeroflex utmc for specific package drawings. package type/ leadcount 1 02 5 05 0 07 5 1 00 15 0 2 00 2 50 3 00 3 50 4 00 4 50 5 00 5 50 6 00 flatpack 68 x x x 84 x x 132 x x 172 x x x x x 196 x x x x x 256 x x x x x x x x x 304 x x x x x x x x x 340 x x x x x x x x x 352 x x x x x pga 2 281 x x x x 299 x x x x lga 472 x x x x
4 extensive cell library the ut0.6 m crh /srh family of gate arrays is supported by an extensive cell library that includes ssi, msi, and 54xx-equiv- alent functions, as well as ram and other library functions. user- selectable options for cell configurations include scan for all reg- ister elements, as well as output drive strength. aeroflex utmc?s core library includes the following functions: intel? 80c31 equivalent intel? 80c196 equivalent mil-std-1553 functions (bcrtm, rti, rtmp) mil-std-1750 microprocessor standard microprocessor peripheral functions configurable ram (sram, dpsram) risc microcontroller usart (82c51) edac refer to aeroflex utmc?s ut0.6 m crh /srh design manual for complete cell listing and details. i/o buffers the ut0.6 m crh /srh gate array family offers up to 544 s ignal i/o locations (note: device signal i/o availability is affected by package selection and pinout.) the i/o cells can be configured by the user to serve as input, output, bidirectional, three-state, or additional power and ground pads. output drive options range from 2 to 1 2m a. to drive larger off-chip loads, output drivers may be combined in parallel to provide additional drive up to 24m a. other i/o buffer features and options include: slew rate control pull-up and pull-down resistors ttl, cmos, and schmitt levels cold sparing voltage translation - 5v bus to 3.3v bus - 3.3v bus to 5v bus jtag boundary-scan the ut0.6 m crh/srh arrays provide for a test access port and boundary-scan that conforms to the ieee standard 1149.1 (jtag). some of the benefits of this capability are: easy test of complex assembled printed circuit boards g ain access to and control of internal scan paths initiation of built-in self test clock driver distribution aeroflex utmc design tools provide methods for balanced clock distribution that maximize drive capability and minimize relative clock skew between clocked devices. speed and performance aeroflex utmc specializes in high-performance circuits de- signed to operate in harsh military and radiation environments. table 3 presents a sampling of typical cell delays. note that the propagation delay for a cmos device is a function of its fanout loading, input slew, supply voltage, operating tem- perature, and processing radiation tolerance. in a radiation environment, additional performance variances must be consid- ered. the ut0.6 m crh /srh array family simulation models account for all of these effects to accurately determine circuit performance for its particular set of use conditions. power dissipation each internal gate or i/o driver has an average power consump- tion based on its switching frequency and capacitive loading. r adiation- tolerant processes exhibit power dissipation that is typical of cmos processes. for a rigorous power estimating methodology, refer to the aeroflex utmc ut0.6 m crh /srh design manual or consult with a aeroflex utmc applications engineer. typical power dissipation 1.1 m w/gate-mhz@5.0v 0.4 m w/gate-mhz@3.3v
5 table 3. typical cell delays note: 1. all specifications in ns (typical). output load capacitance is 50pf. fanout loading for input buffers and gates is the equivalen t of two gate input loads. cell output transition propagation delay 1 internal gates v dd = 5.0v v dd = 3.3v inv1, inverter hl .1 5 .16 lh . 23 .29 inv4, inverter 4x hl . 06 .07 lh .1 0 .16 nand2, 2-input nand hl . 1 9 .25 lh . 22 .33 nor2, 2-input nor hl .1 6 .22 lh . 32 .45 dff - clk to q hl .81 1.12 lh .76 1.06 hl .75 1.05 lh . 6 1 .85 output buffers oc5050n4, cmos hl 3.85 2.15 lh 4.66 3.76 ot5050n4, ttl, 4ma hl 5. 58 5.49 lh 2.52 2.93 ot5050n12, ttl, 12ma hl 2.42 lh 1.29 input buffers ic5050, cmos hl .81 1.07 lh 1.16 1.18 it5050, ttl hl 1.39 1.12 lh 1.16 1.30
6 asic design software using a combination of state-of-the-art third-party and proprietary design tools, aeroflex utmc delivers the cae support and capability to handle complex, high-performance asic designs from design concept through design verification and test. aeroflex utmc?s flexible circuit creation methodology supports high level design by providing ut0.6 m crh/srh libraries for mentor graphics and synopsys synthesis tools. design verification is performed in any vhdl or verilog simulator or the mentor graphics environment, using aeroflex utmc?s robust libraries. aeroflex utmc also supports automatic test program generation to improve design testing. aeroflex utmc hdl design systems aeroflex utmc offers a hardware description language (hdl) design system supporting vhdl and verilog. both the vhdl and verilog libraries provide sign-off quality models and robust tools. the vhdl libraries are vital 3.0 compliant, and the verilog libraries are ovi 1.0 compliant.with the library capabilities aeroflex utmc provides, you can use high level design methods to synthesize your design for simulation. aeroflex utmc also provides tools to verify that your hdl design will result in working asic devices. either of aeroflex utmc?s hdl design system lets you easily access aeroflex utmc?s radhard capabilities. advantages of the aeroflex utmc hdl design systems ? the aeroflex utmc hdl design system gives you the freedom to use tools from synopsys, mentor graphics, cadence, view logic , and other vendors to help you synthesize and verify a design. ? aeroflex utmc?s logic rules checker and tester rules checker allow you to verify partial or complete designs for compliance with aeroflex utmc design rules. ? aeroflex utmc hdl design system accepts back- annotation of timing information through sdf. ? your design stays entirely within the language in which you started (vhdl or verilog) preventing conversion headaches. xdt sm (external design translation) through aeroflex utmc?s xdt services, customers can convert an existing non- aeroflex utmc design to aeroflex utmc?s processes. the xdt tool is particularly useful for converting an fpga to a aeroflex utmc radiation-tolerant gate array. the xdt translation tools convert industry standard netlist formats and vendor libraries to aeroflex utmc formats and libraries. industry standard netlist formats supported by aeroflex utmc include: ? vhdl ? verilog hdl tm ? fpga source files (actel, altera, xilinx) ? edif ? third-party netlists supported by synopsys mentor modelsim h dl tool supplier completed asic design cadence leapfro g/ verilog xl view logic speedwave/ vcs synopsys vss /vcs high level design activities utmc h dl design system aeroflex utmc h dl design flow
7 aeroflex u tmc mentor graphics design system the aeroflex utmc mentor graphics design system software is fully integrated into the mentor graphics design environment, making it familiar and easy to use. aeroflex utmc tools support mentor functions such as cross- highlighting, graphical menus, and design navigation. after creating a design in the mentor graphics environment, you can easily verify the design for electrical rules compliance with the aeroflex utmc logic rules checker. testability can be verified with the aeroflex utmc tester rules checker. both of these tools are fully integrated into the mentor graphics environment. when you have completed all design activities, aeroflex utmc?s design transfer tool captures all the required files and prepares them for easy transfer to aeroflex utmc. aeroflex utmc uses this data to convert your design into a packaged and tested device. advantages of the aeroflex utmc mentor design system ? aeroflex utmc customers have successfully used the aeroflex utmc mentor graphics design system for over a decade. ? aeroflex utmc?s logic and tester rules checker tools allow you to verify partial or complete designs for compliance with aeroflex utmc manufacturing practices and procedures. ? the design system accepts pre-and post-layout timing information to ensure your design results in devices that meet your specifications. ? the design system supports leonardo, and database transfer between synopsys and mentor. ? the design system supports powerful mentor graphics atpg capabilities . tools supported by aeroflex utmc aeroflex utmc supports libraries for: ? mentor graphics ? modelsim ? synopsys ? design compiler ? primetime ? formality ? tetramax ? vital-compliant vhdl tools ? ovi-compliant verilog tools training and support aeroflex utmc personnel conduct training classes tailored to meet individual needs. these classes can address a wide mix of engineering backgrounds and specific customer concerns. applications assistance is also available through all phases of asic design. design manufacturing utmc mentor design system translate an external design convert an fpga schematic entry synthesis design idea aeroflex utmc mentor graphics design
8 physical design using three layers of metal interconnect, aeroflex utmc achieves optimized layouts that maximize speed of critical nets, overall chip performance, and design density up to 600,000 equivalent gates. test capability aeroflex utmc supports all phases of test development from test stimulus generation through high-speed production test. this support includes atpg, fault simulation, and fault grading. scan design options are available on all ut0.6 m crh /srh storage elements. automatic test program development capabilities han- dle large vector sets for use with aeroflex utmc?s ltx/ trillium micromasters, supporting high-speed testing (up to 80mhz with pin multiplexing). unparalleled quality and reliability aeroflex utmc is dedicated to meeting the stringent perfor- mance requirements of aerospace and defense systems suppliers. aeroflex utmc maintains the highest level of quality and reli- ability through our quality management program under mil- prf-38535 and iso-9001. in 1988, we were the first gate array manufacturer to achieve qpl certification and qualification of our technology families. our product assurance program has kept pace with the demands of certification and qualification. our quality management plan includes the following activities and initiatives. quality improvement plan failure analysis program spc plan corrective action plan change control program standard evaluation circuit (sec) and technology charac- terization vehicle (tcv) assessment program certification and qualification progra m b ecause of numerous product variations permitted with customer specific designs, much of the reliability testing is performed us- ing a standard evaluation circuit (sec) and technology characterization vehicle (tcv). the tcv utilizes test structures to evaluate hot carrier aging, electromigration, and time depen- dent test samples for reliability testing. data from the wafer-level testing can provide rapid feedback to the fabrication process, as well as establish the reliability performance of the product before it is packaged and shipped. radiation tolerance aeroflex utmc incorporates radiation-tolerance techniques in process design, design rules, array design, power distribution, and library element design. all key radiation- tolerance process parameters are controlled and monitored using statistical meth- ods and in-line testing. notes: 1. total dose co-60 testing is in accordance with mil-std-883, method 1019. data sheet electrical characteristics guaranteed to 1.0e5 rads(si o 2 ). a ll post-radiation values measured at 25 c. 2. total dose co-60 testing is in accordance with mil-std-883, method 1019 at dose rates <1 rad(si o 2 )/s. 3. short pulse 20ns fwhm (full width, half maximum). 4. is design dependent; seu limit based on standard evaluation circuit at 4.5v worst case condition. 5. seu-hard flip-flop cell. non-hard flip-flop typical is 4e-8. parameter radiation tolerance notes total dose 1.0e5 rad ( si o 2 ) 3.0e5 rad(sio 2 ) 1 2 dose rate upset 1.0e 8 rad ( si )/ sec 3 dose rate survivability 1.0e1 1 rad ( s i)/ sec 4 seu < 2 .0e-10 errors per cell-day 4, 5 projected neutron fluence 1.0e14 n/sq cm latchup latchup-immune over speci- fied use conditions
9 absolute maximum ratings 1 (referenced to v ss ) note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions symbol parameter limits v dd dc supply voltage -0.3 to 6.0v v i/o voltage on any pin -0.3v to v dd + 0.3 t stg storage temperature -65 to +150 c t j maximum junction temperature +175 c i lu latchup immunity + 150ma i i dc input current + 10ma t ls lead temperature (soldering 5 sec) +300 c symbol parameter limits v dd positive supply voltage 3.0 to 5.5v t c case temperature range -55 to +125c v in dc input voltage 0v to v dd
10 dc electrical characteristics (v dd = 5.0v + 10%; -55 c < t c < +125 c) symbol parameter condition min typ max unit v il low-level input voltage 1 ttl inputs cmos v dd = 4.5v and 5.5v 0.8 .3v dd v v ih high-level input voltage 1 ttl inputs cmos v dd = 4.5v and 5.5v 2.2 .7v dd v v t + schmitt trigger, positive going 1 threshold v dd = 4.5v and 5.5v .7 v dd v v t - schmitt trigger, negative going 1 threshold v dd = 4.5v and 5.5v .3 v dd v v h schmitt trigger, typical range of hysteresis 2 0.6 v i in input leakage current ttl, cmos, and schmitt inputs inputs with pull-down resistors inputs with pull-down resistors inputs with pull-up resistors inputs with pull-up resistors cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 5.5v v in = v dd and v ss v in = v dd v in = v ss v in = v ss v in = v dd v in = 0 to 5.5v v dd = v ss = 0v v in = v and 5.5v -1 + 20 - 5 - 225 - 5 -5 -5 1 + 225 +5 -20 + 5 +5 +5 m a v ol low-level output voltage 3 ttl 2.0ma buffer ttl 4.0ma buffer ttl 8.0ma buffer ttl 12.0ma buffer * cmos outputs cmos outputs (optional) cmos outputs (cold spare) v dd = 4.5v i ol = 2.0ma i ol = 4.0ma i ol = 8.0ma i ol = 12.0ma i ol = 1.0 m a i ol = 100 m a i ol = 100 m a 0.4 0.4 0.4 0.4 0.05 0.25 0.25 v v oh high-level output voltage 3 ttl 2.0ma buffer ttl 4.0ma buffer ttl 8.0ma buffer ttl 12.0ma buffer * cmos outputs cmos outputs (optional) cmos outputs (cold spare) v dd = 4.5v i oh = -2.0ma i oh = -4.0ma i oh = -8.0ma i oh = -12.0ma i oh = -1.0 m a i oh = -100 m a i oh = -100 m a 2.4 2.4 2.4 2.4 v dd -0.05 v dd -0. 3 5 v dd -0.3 5 v
11 symbol parameter condition min typ max unit i oz three-state output leakage current ttl 2.0ma buffer ttl 4.0ma buffer, cmos ttl 8.0ma buffer ttl 12.0ma buffer * cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 5.5v v o = 0v and 5.5v v dd = v ss = 0 v dd = 0 to 5.5v - 5 -10 -20 -3 0 -5 -5 5 10 20 30 -5 -5 m a i os short-circuit output current 2 ,4 ttl 2.0ma buffer ttl 4.0ma buffer, cmos t tl 8.0ma buffer ttl 12.0ma buffer * v o = 0v and 5.5v -50 -100 -200 -300 50 100 200 300 ma i ddq quiescent supply current 6 group a subgroups 1,3 v dd = 5.5v 200k gates 400k gates 600k gates 50 100 180 m a group a subgroup 2 v dd = 5.5v 200k gates 400k gates 600k gates 1 2 3 ma group a, subgroup 1 rha designator: m, d, p, l, r v dd = 5.5v 200k gates 400k gates 600k gates 4 8 12 ma c in input capacitance 5 17 pf c out output capacitance 5 ttl 2.0ma buffer ttl 4.0ma buffer ttl 8.0ma buffer , cmos ttl 12.0ma buffer * 1 7 1 7 1 8 2 3 pf c io bidirect i/o capacitance 5 ttl 4.0ma buffer ttl 8.0ma buffer , cmos ttl 12.0ma buffer * 1 6 1 9 2 3 pf
12 notes: * contact aeroflex utmc prior to usage. 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input volta ge within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density < 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pf*mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz @0v and a signal amplitude of < 50mv rms. 6. all inputs with internal pull-ups should be left floating. all other inputs should be tied high or low.
13 dc electrical characteristics (v dd = 3.3v + .3v; -55 c < t c < +125 c) symbol parameter condition min typ max unit v il low-level input voltage 1 cmos v dd = 3.0v and 3.6v .3v dd v v ih high-level input voltage 1 cmos v dd = 3.0v and 3.6v .7v dd v v t + schmitt trigger, positive going 1 threshold v dd = 3.0v and 3.6v .7v dd v v t - schmitt trigger, negative going 1 threshold v dd = 3.0v and 3.6v .3v dd v v h schmitt trigger, typical range of hysteresis 2 . 6 v i in input leakage current ttl, cmos, and schmitt inputs inputs with pull-down resistors inputs with pull-down resistors inputs with pull-up resistors inputs with pull-up resistors cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 3.6v v in = v dd and v ss v in = v dd v in = v ss v in = v ss v in = v dd v in = 0 to 3.6v v dd = v ss = 0v v in = v and 3.6v -1 +10 - 5 - 225 -5 -5 -5 1 + 225 +5 -1 0 +5 +5 +5 m a v ol low-level output voltage cmos outputs cmos outputs (optional) cmos outputs (cold spare) i ol = 1.0 m a i ol = 100 m a i ol = 100 m a 0.05 0.25 0.25 v v oh high-level output voltage cmos outputs cmos outputs (optional) cmos outputs (cold spare) i oh = -1.0 m a i oh = -100 m a i oh = -100 m a v dd -0.05 v dd -0. 3 5 v dd -0.35 v
14 notes: * contact aeroflex utmc prior to usage. 1. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input volta ge within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit but not guaranteed or tested. 3. per mil-prf-38535, for current density < 5.0e5 amps/cm 2 , the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pf*mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz @0v and a signal amplitude of < 50mv rms. 6. all inputs with internal pull-ups should be left floating. all other inputs should be tied high or low. symbol parameter condition min typ max unit i oz three-state output leakage current cmos cold spare inputs - normal mode cold spare inputs - cold spare mode v dd = 3.6v v o = v dd and v ss v dd = v ss = 0v v o = 0v and 3.6v -20 -5 -5 20 5 5 m a i os short-circuit output current 2 ,4 cmos v o = v dd and v ss -200 200 ma i ddq quiescent supply current 6 group a subgroups 1,3 v dd = 5.5v 200k gates 400k gates 600k gates 50 100 180 m a group a subgroup 2 v dd = 5.5v 200k gates 400k gates 600k gates 1 2 3 ma group a, subgroup 1 rha designator: m, d, p, l, r v dd = 5.5v 200k gates 400k gates 600k gates 4 8 12 ma c in input capacitance 5 1 7 pf c out output capacitance 5 cmos 1 8 pf c io bidirect i/o capacitance 5 cmos 1 9 pf
15 hp/apollo and hp-ux are registered trademarks of hewlett-packard, inc. intel is a registered trademark of intel corporation mentor, mentor graphics, autologic ii, quicksim ii, quickfault ii, quickhdl, quickgrade ii, fastscan, flextest and dft advisor a re registered trademarks of mentor graphics corporation sun is a registered trademark of sun microsystems, inc. verilog and leapfrog are registered trademarks of cadence design systems, inc. synopsys, design compiler, test compiler plus, vhdl compiler, verilog hdl compiler, testsim and vss are trademarks of synopsys, inc. vantage is a trademark of viewlogic
16 notes

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